A memory may have a power saving mode in which certain portions of the memory are deactivated to reduce leakage. However, typical power saving modes require a long time to wake up to the normal operating mode, and this long latency of wakeup time is not practical for many applications which need to access the memory in short intervals. Often a device using the memory cannot afford to wait many cycles for the memory to wake up from the power saving mode. While prediction schemes could be used to signal that the memory should begin to wake up many cycles earlier than it is actually required, this typically requires complicated or infeasible prediction schemes, which are difficult to implement in a real system. Therefore, in practice many memories do not use any intermediate leakage saving modes. Often the only power saving mode which is actually used in practice is a full power down mode in which the entire memory is switched off, which has a very long wakeup time and so is suitable only when the processor is also powered down.
Hence, the present technique seeks to provide a power saving mode with a faster wakeup time than existing power saving modes.